Our paper “The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog” has been accepted by OOPSLA’23.
Congratulations to Qinlin, Nairen, and Jinpeng!
This is our first published research work on EDA and hardware description language.
May 25, 2023
Our paper “Tai-e: A Developer-Friendly Static Analysis Framework for Java by Harnessing the Good Designs of Classics” has been accepted by ISSTA’23.
Congratulations to Tian and Yue! (ᕑᗢᓫ∗)˒
This paper describes the designs for the major components of Tai-e.
April 01, 2023
Our paper “Context Sensitivity without Context: A Cut-Shortcut Approach to Fast and Precise Pointer Analysis” has been accepted by PLDI’23.
Congratulations to Wenjie and Shengyuan!
This is the first published research work developed on top of Tai-e.
July 31, 2022
Tai-e, an easy-to-learn, easy-to-use, efficient, and extensible static analysis framework for Java, has been released at GitHub! Please refer to our technical report for details.